A bicmos device having a cmos gate electrode and a bipolar emitter each containing two imurities of the same conductivity type

ABSTRACT

A semiconductor device and a method of producing the same are disclosed. After boron or similar p-type impurity has been introduced into a polysilicon layer constituting a pMOS gate, annealing can be effected at an optimal temperature low enough to prevent the impurity from entering a silicon substrate via a gate oxide film, e.g., 800° C. or below in the case of boron. This prevents the characteristic of a transistor, e.g., threshold voltage from being varied. Further, in an nMOS gate electrode and source-drain region, the n-type impurity can be provided with a concentration reducing the resistance of a silicide layer. In addition, in the emitter diffusion layer of a bipolar transistor, the concentration of the n-type impurity does not fall and allows a current amplification factor to be increased while allowing an emitter resistance to be reduced.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a semiconductor device having aCMOS (Complementary Metal Oxide Semiconductor) transistor and a bipolartransistor formed on a single substrate and, more particularly, to acomposite LSI (Large Scale Integrated Circuit) having the gate electrodeof a MOS transistor and the emitter electrode of a bipolar transistorformed by sharing the same layers, and a method of producing the same.

[0002] Today, BiCMOS technologies are available for forming a bipolartransistor having a high current drive capability and a CMOS transistorfeasible for high integration on a single chip. A BiCMOS structure isattracting increasing attention as an implementation for a small power,high speed LSI including both of digital and analog circuitry. However,a conventional BiCMOS procedure is undesirable from the cost standpointbeause it involve a great number of steps. Although various approachesto save the production steps have been proposed in the past, they havesome problems left unsolved.

SUMMARY OF THE INVENTION

[0003] It is therefore an object of the present invention to provide asemiconductor device having a desirable characteristic, and a method ofproducing the same.

[0004] In accordance with the present invention, in a semiconductordevice having a CMOS transistor and a bipolar transistor formed on asingle semiconductor substrate, a gate electrode and an emitterelectrode included in the CMOS transistor and bipolar transistor,respectively, are formed by sharing the same polysilicon layers. Animpurity contained in an nMOS gate electrode and an emitter electrode ofthe bipolar transistor has a lower concentration than an emitterdiffusion layer formed in the intrinsic base region of the bipolartransistor.

[0005] Also, in accordance with the present invention, a method ofproducing a semiconductor device has the steps of forming an emittercontact hole, introducing an impurity via the emitter contact hole byion implantation to thereby form an emitter diffusion region, forming agate electrode and an emitter electrode of a MOS transistor, effectingformation of an nMOS source-drain and introduction of an impurity intoan emitter electrode of a bipolar transistor at the same time, effectingfirst annealing, effecting formation of a pMOS source-drain andintroduction of an impurity into an extrinsic base region of the bipolartransistor at the same time, and effecting second annealing.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The above and other objects, features and advantages of thepresent invention will become apparent from the following detaileddescription taken with the accompanying drawings in which:

[0007] FIGS. 1A-1D are sections showing a conventional method ofproducing a semiconductor device;

[0008]FIG. 2 is a graph showing a relation between the dose of arsenicand the resistance of a silicide layer for describing the problems ofthe conventional method;

[0009] FIGS. 3A-3D are sections showing a procedure for producing asemiconductor device embodying the present invention;

[0010]FIG. 4 is a section showing the semiconductor device produced bythe procedure of FIGS. 3A-3D; and

[0011] FIGS. 5A-5D are sections showing an alternative embodiment of thepresent invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] To better understand the present invention, brief reference willbe made to a conventional method of producing a semiconductor device,shown in FIGS. 1A-1D. The semiconductor device has a BiCMOS structurecustomarily used to reduce the number of production steps.

[0013] First, as shown in FIG. 1A, an n-type epitaxial layer 4 is formedon a semiconductor substrate 1 having an n-type and a p-type buriedlayer 2 and 3 thereinside. A field oxide layer 5 is formed on theepitaxial layer 4 by conventional LOCOS (Local Oxidation of Silicon).Subsequently, there are formed an n-type well region 6 and a p-type wellregion 7 as well as an n-type collector lead-out region 8 and anintrinsic base region 9 of a bipolar transistor. Just after a gate oxidefilm of a MOS transistor has been formed to a thickness of 5 nm to 20nm, a polysilicon layer 27 is formed on the gate oxide film 10 to athickness of 50 nm to 100 nm. When an emitter contact hole is formed, aswill be described, the polysilicon layer 27 is used to protect the gateoxide film 10 from defective breakdown voltage ascribable tocontamination and damage.

[0014] As shown in FIG. 1B, the polysilicon layer 27 and gate oxide film10 are etched in order to form an emitter contact hole 12. Then, apolysilicon layer 28 is formed over the entire surface of the substrate1 to a thickness of 100 nm to 200 nm.

[0015] As shown in FIG. 1C, the polysilicon layers 28 and 27 are etchedin order to form a gate electrode 15 of an nMOS transistor, a gateelectrode 16 of a pMOS transistor, and an emitter electrode 17 of thebipolar transistor. After a 100 nm to 150 nm thick oxide film has beenformed, side walls 18 are respectively formed around the gate electrodes15 and 16 and emitter electrode 17 by anisotropic dry etching.Subsequently, boron ions are implanted in a source-drain region 19 a ofthe pMOS transistor, the gate electrode 16 and an outside base region 19b of the bipolar transistor by acceleration energy of 10 keV and in adose of 5×10¹⁵ cm⁻² to 7×10¹⁵ cm⁻². On the other hand, arsenic ions areimplanted in a source-drain region 20 of the nMOS transistor, the gateelectrode 15, and the emitter electrode 17 of the bipolar transistor byacceleration energy of 30 keV and in a dose of 1×10¹⁶ cm⁻² to 2×10¹⁶cm⁻². The resulting laminate is annealed at 850° C. to 900° C. in anitrogen atmosphere in order to to activate the implanted impurities.Specifically, in the gate electrode 16 of the pMOS transistor, boron isdiffused from the upper polysilicon layer 28 to the lower polysiliconlayer 27, forming a p-type gate electrode. Likewise, in the gateelectrode of the nMOS transistor, arsenic is diffused from the upperpolysilicon layer 28 to the lower polysilicon layer 27, forming ann-type gate electrode. Further, in the emitter electrode 17 of thebipolar transistor, arsenic is diffused from the upper polysilicon layer28 to the lower polysilicon layer 27 and intrinsic base region 9,forming an emitter diffusion region 21.

[0016] Thereafter, as shown in FIG. 1D, an interlayer dielectric film 22is formed on the entire surface of the substrate produced by the aboveprocedure. Then, contacts are opened in the dielectric film 22, andplugs 23 are formed by use of, e.g., tungsten. Finally, metal wirings 24are formed, completing a semiconductor device.

[0017] As stated above, to save the production steps, the gateelectrodes 15 and 16 of the MOS transistors and the emitter electrode 17of the bipolar transistor are formed by sharing the polysilicon layers27 and 28. Further, to simplify the production, the source-drain region19 a of the pMOS transistor and the outside base region 19 b of thebipolar transistor are formed by a single step. In addition, the theformation of the source-drain region 20 of the nMOS transistor and theimplantation of the impurity in the emitter electrode 17 of the bipolartransistor are effected by a single step.

[0018] The part of the above specific BiCMOS structure relating only tothe bipolar transistor is disclosed in, e.g., Japanese PatentPublication No. 7-44184 specifically.

[0019] However, the conventional semiconductor device and procedure forproducing it have the following disadvantages. The p-type electrodeportion of the pMOS transistor is implemented by the implantation anddiffusion of boron in the upper polysilicon layer 28, as stated above.In the p-type electrode portion, boron diffused to the lower siliconlayer 27 is further diffused to the silicon substrate 1 via the gateoxide film 10, resulting in the variation of the threshold voltage ofthe pMOS transistor. Moreover, such penetration of boron is acceleratedby the annealing atmosphere and temperature and fluorine present inpolysilicon. This aggravates limitation on the production conditionsafter the introduction of boron into the gate electrode.

[0020] On the other hand, a silicide layer formed by the silicidation ofthe nMOS gate electrode 15 has a resistance noticeably susceptible tothe dose of arsenic implanted in the polysilicon layer, as shown in FIG.2. As shown, so long as the dose of arsenic is as small as 1×10¹⁵ cm⁻²to 3×10¹⁵ cm⁻², a desirable silicide layer with low resistance isachievable. However, when the dose increases to 1×10¹⁶ cm⁻² to 2×10¹⁶cm⁻², silicidation is obstructed with the result that the silicide filmhas its thickness reduced and therefore has its resistance increased toa noticeable degree. It is therefore optimal to implant about 1×10¹⁵cm⁻² to 3×10¹⁵ cm⁻² of arsenic in the gate electrode and source-drainregion of the nMOS portion in order to reduce the resistance of thesilicide layer.

[0021] Assume that the impurity introduced into the polysilicon layer ofthe emitter portion included in the bipolar transistor has aconcentration of, e.g., about 1×10¹⁵ cm⁻² to 3×10¹⁵ cm⁻² as low as inthe nMOS gate electrode 15. Such a small amount of emitter impuritycauses the impurity to decrease around the emitter contact (generallyreferred to as a plugging effect). This brings about a decrease incurrent amplification factor and an increase in emitter resistance aswell as other defects. In this manner, the optimal dose of impurity forthe nMOS transistor and the optimal dose of impurity for the bipolartransistor are different from each other.

[0022] In light of the above, the impurity may be implanted in each ofthe gate electrode and source-drain region of the nMOS transistor andthe emitter electrode of the bipolar transistor independently, each inan optimal dose. This, however, increases the number of productionsteps.

[0023] Referring to FIGS. 3A-3D, a procedure for producing asemiconductor device embodying the present invention will be described.As shown in FIG. 3A, an n-type epitaxial layer 4 is formed on asemiconductor substrate 1 having an n-type and a p-type buried layer 2and 3 therein. A field oxide layer 5 is formed on the substrate 1 byLOCOS. Subsequently, an n-type well region 6 and a p-type well region 7and an n-type collector lead-out region 8 and an in intrinsic baseregion 9 of a bipolar transistor are formed. Then, just after a gateoxide film 10 of a MOS transistor has been formed to a thickness of 5 nmto 20 nm, a polysilicon layer 11 is formed to a thickness of 50 nm to100 nm.

[0024] As shown in FIG. 3B, photoresist 13 is formed on the polysiliconlayer 11 and then patterned. Subsequently, the polysilicon layer 11 isetched in the emitter region of the bipolar transistor with thepatterned photoresist 13 playing the role of a mask, thereby forming anemitter contact hole 12. Then, an n-type impurity is introduced into theintrinsic base region 9 via the emitter contact hole 12 by ionimplantation. Assuming that the n-type impurity is implemented byarsenic, then the acceleration energy and dose are respectively selectedto be 30 keV and 5×10¹⁴ cm⁻² to 1×10¹⁶ cm⁻². Arsenic may, of course, bereplaced with antimony or phosphor.

[0025] After the gate oxide film 10 is etched and stripped as shown inFIG. 3C, a 100 nm to 200 nm thick polysilicon layer 14 is formed overthe entire surface of the substrate 1.

[0026] Assume that the n-type impurity introduced into the intrinsicbase region 9 has a surface concentration above, e.g., about 1×10²⁰cm⁻³. Then, when the substrate 1 is conveyed into a CVD (Chemical VaporDeposition) apparatus in order to grow the polysilicon layer 14, it islikely that oxygen (air) around the inlet of the CVD apparatus entersthe apparatus and forms an oxide film on the exposed n-type impuritylayer. This oxide film makes it difficult to set up desirable contactbetween the polysilicon layer 14 and the n-type diffusion layer. Thisproblem will be solved if used is made of a so-called load-lock typepolysilicon growth apparatus in which a substrate is introduced into avacuum chamber and then into a growth chamber. Alternatively, theextremely thin oxide film may be removed by reduction using hydrogen gasbefore the growth of the polysilicon layer 14 to be effected in a growthchamber.

[0027] As shown in FIG. 3D, the polysilicon layers 14 and 11 are etchedin order to form a gate electrode 15 of an nMOS transistor, a gateelectrode 16 of a pMOS transistor, and an emitter electrode 17 of thebipolar transistor. Subsequently, a 100 nm to 150 nm thick oxide film isformed and then subjected to dry etching so as to form side walls 18around the gate electrodes 15 and 16 and emitter electrode 17.Thereafter, arsenic ions are implanted in a source-drain region 20 andgate electrode 15 of the nMOS region and the emitter electrode 17 of thebipolar transistor by acceleration energy of 30 keV and in a doze of3×10¹⁵ cm⁻². The resulting substrate is annealed in a nitrogenatmosphere at 900° C. in order to activate the implanted impurity.Specifically, in the gate electrode 15 of the pMOS transistor, arsenicis diffused from the upper polysilicon layer 14 to the lower polysiliconlayer 11, forming an n-type gate electrode. Likewise, in the emitterelectrode 17 of the bipolar transistor, arsenic is diffused from theupper polysilicon layer 14 to the lower polysilicon layer 11, formingthe emitter electrode 17.

[0028] Further, boron ions are implanted in the source-drain region 19 aand gate electrode 16 of the pMOS transistor and an outside base region19 b of the bipolar transistor by acceleration energy of 10 keV and in adoze of 5×10¹⁵ cm⁻² to 7×10¹⁵ cm⁻². This impurity is activated in anitrogen atmosphere at 800° C. Specifically, in the gate electrode 16,boron is diffused from the upper polysilicon layer 14 to the lowerpolysilicon layer 11, forming a p-type gate electrode. After aninterlayer dielectric film 22 has been formed on the substrate producedby the above produce, contacts are formed in the dielectric film 22, andthen plugs 23 are formed by use of tungsten. Finally, metal wirings 24are formed to complete a semiconductor device shown in FIG. 4.

[0029] In the illustrative embodiment, the gate electrode and emitterelectrode are formed by sharing the same polysilicon layers, and theformation of the source-drain of the nMOS transistor and the impurityimplantation in the emitter electrode of the bipolar transistor areeffected by a single step. This, however, does not bring about thepreviously mentioned troubles including a decrease in currentamplification factor and an increase in emitter resistance, because anemitter diffusion layer is formed beforehand to implement an optimal lown-type impurity concentration for the silicidation of the nMOS gateelectrode. Further, in the illustrative embodiment, the source-train ofthe pMOS transistor and the extrinsic base region of the bipolartransistor are formed by a single step. Nevertheless, because annealingnecessary for the nMOS transistor and the emitters of the bipolartransistor is effected before the above step, annealing following theboron implantation can be effected at a temperature low enough toobviate the penetration of boron, e.g., 800° C. or below.

[0030] Reference will be made to FIGS. 5A-5D for describing analternative embodiment of the present invention. This embodiment isessentially similar to the previous embodiment except for the following.After the polysilicon layer 11 and gate oxide film 10 have been etchedin the emitter region of the bipolar transistor in order to form theemitter contact film 12, the n-type impurity is introduced into theintrinsic base region 9 by ion implantation. At this instant, thisembodiment removes the photoresist mask used to form the contact hole12, and then implants the n-type impurity over the entire surface of thesubstrate 1. As a result, the n-type impurity introduced into the lowerpolysilicon layer 11 captures the boron atoms. This embodiment istherefore capable of obstructing the penetration of boron more than theprevious embodiment. Another advantage achievable with this embodimentis that in the nMOS transistor the above n-type impurity is added to then-type impurity introduced into the gate electrode at the time offormation of the source-drain, obstructing depletion in the nMOS gateelectrode. The n-type impurity to be introduced into the lowerpolysilicon layer 11 may be implemented by arsenic, phosphor, antimonyor similar substance. Among them, phosphor is optimal because itobstructs the penetration of boron due to little segregation to thegrain boundary portions of polysilicon even with a low concentration.

[0031] Specifically, the step shown in FIG. 5A is identical with thestep described with reference to FIG. 3A. In the illustrativeembodiment, as shown in FIG. 5B, the polysilicon layer 11 and gate oxidefilm 10 are etched in the emitter region of the bipolar transistor inorder to form the emitter contact hole 12. Subsequently, the photoresistmask used to form the hole 12 is removed, and then an n-type impurity isimplanted in the intrinsic base region 9 over the entire surface of thesubstrate 1. For ion implantation, use may be made of accelerationenergy of 5 keV and a dose of 1×10¹⁵ cm⁻² to 1×10¹⁶ cm⁻² by way ofexample. If desired, the n-type impurity may be implemented by antimonyor arsenic.

[0032] The steps shown in FIGS. 5C and 5D are respectively identicalwith the steps described with reference to FIGS. 3C and 3D and will notbe described in order to avoid redundancy. The resulting semiconductordevice also has the configuration shown in FIG. 4.

[0033] In any one of the above embodiments, the emitter diffusion layer21 provided in the substrate 1 may be constituted by two or moredifferent kinds of impurities. For example, assume that the n-typeimpurity to be introduced by ion implantation is antimony while then-type impurity to be introduced into the polysilicon layer of theemitter electrode 17 is phosphor. Then, the resulting substrate may beannealed at 900° C. to 800° C. in order to diffuse phosphor frompolysilicon into the substrate 1 and further diffuse it to cover theantimony junction. This can be done because antimony in silicon has adiffusion constant smaller than the diffusion constant of phosphor byabout two figures. If the antimony junction having such a small impuritydiffusion constant and a sharp impurity distribution is covered withphosphor having a relatively great impurity diffusion constant and arelatively gentle impurity distribution, then it is possible to ease anelectric field between the base and the emitter. With this kind ofconfiguration, a base-emitter breakdown voltage 2 V to 3 V higher thanone available with only antimony is achievable.

[0034] In summary, in accordance with the present invention, after boronor similar p-type impurity has been introduced into a polysilicon layerconstituting a pMOS gate, annealing can be effected at an optimaltemperature low enough to prevent the impurity from entering a siliconsubstrate via a gate oxide film, e.g., 800° C. or below in the case ofboron. This prevents the characteristic of a transistor, e.g., thresholdvoltage from being varied. Further, in an nMOS gate electrode andsource-drain region, the n-type impurity can be provided with aconcentration reducing the resistance of a silicide layer. In addition,in the emitter diffusion layer of a bipolar transistor, theconcentration of the n-type impurity does not fall and allows a currentamplification factor to be increased while allowing an emitterresistance to be reduced.

[0035] Various modifications will become possible for those skilled inthe art after receiving the teachings of the present disclosure withoutdeparting from the scope thereof.

What is claimed is:
 1. In a semiconductor device having a CMOStransistor and a bipolar transistor formed on a single semiconductorsubstrate, a gate electrode and an emitter electrode included in saidCMOS transistor and said bipolar transistor, respectively, are formed bysharing same polysilicon layers, and an impurity contained in an nMOSgate electrode and an emitter electrode of said bipolar transistor has alower concentration than an emitter diffusion layer formed in anintrinsic base region of said bipolar transistor.
 2. A semiconductordevice as claimed in claim 1, wherein two kinds of impurities areintroduced in said emitter diffusion layer.
 3. A method of producing asemiconductor device, comprising the steps of: forming an emittercontact hole; introducing an impurity via said emitter contact hole byion implantation to thereby form an emitter diffusion region; forming agate electrode and an emitter electrode of a MOS transistor; effectingformation of an nMOS source-drain and introduction of an impurity intoan emitter electrode of a bipolar transistor at the same time; effectingfirst annealing; effecting formation of a pMOS source-drain andintroduction of an impurity into an extrinsic base region of saidbipolar transistor at the same time; and effecting second annealing. 4.A method as claimed in claim 3, wherein said second annealing iseffected at a lower temperature than said first annealing.
 5. A methodas claimed in claim 3, wherein said gate electrode and said emitterelectrode are formed by sharing same polysilicon layers, said methodfurther comprising removing, just before a growth of a polysilicon layerfor said gate electrode and said emitter electrode, an oxide film formedon a surface of a substrate and exposed via said emitter contact hole ina growth apparatus.